The primary objective of the PandA project is to develop a usable framework that will enable the research of new ideas in the HW-SW Co-Design field.
The PandA framework includes methodologies supporting the research on high-level synthesis of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software partitioning and mapping, on metrics for performance estimation of embedded software applications and on dynamic reconfigurable devices.
The source files currently distributed mainly cover the high-level synthesis of C based descriptions.
Patches and pull request could be submitted at GitHub while stable releases are available for download through this link.
For further information send an e-mail to firstname.lastname@example.org or visit the google group page
The following support is gratefully acknowledged:
- Xilinx through the donation of two Nexys4 boards and for full licenses of Vivado Design suite.
- Altera through the donation of many DE1 CycloneII boards, one DE1-SOC and for a full license of Quartus software.
- European Union for funding some of this work through this list of projects:
- ICODES – Interface and Communication based Design of Embedded Systems
- hArtes – Holistic Approach to Reconfigurable Real Time Embedded Systems
- Synaptic – SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms
- Faster – Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
- European Space Agency for funding some of this work through this list of contracts:
- ESA/ESTEC/Contract N. 4000100797 – Development of methodologies and tools for predictable, real-time LEON-DSP based embedded systems.
- ESA/ESTEC/Contract No. 22167/09/NL/JK. Cache Optimization for LEON Analysis (COLA).
- ESA/ESTEC/Contract Call-Off Order 4 “Multicore and Schedulability Analysis” for TASTE project.